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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 3
Configuration for ×16 components, TFBGA-84 (top view)
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Notes
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ
are isolated on the device.
Rev. 1.50, 2007-12
16
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
