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HYB18T256400AFL-3.7 参数 Datasheet PDF下载

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型号: HYB18T256400AFL-3.7
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分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 63 页 / 3597 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T256[40/80/16]0A[C/F](L)  
256-Mbit Double-Data-Rate-Two SDRAM  
3.2  
Extended Mode Register EMR(1)  
The Extended Mode Register EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency,  
OCD program, ODT, DQS and output buffers disable, RDQS and RDQS enable.  
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TABLE 12  
Extended Mode Register Definition, BA2:0 = 001B  
Field  
Bits Type1)  
Description  
Bank Address 2  
Note: BA2 not available on 256 Mbit and 512 Mbit components  
0B BA2 Bank Address  
Bank Address 1  
BA2  
16  
reg. addr.  
BA1  
BA0  
A13  
15  
14  
13  
0B  
BA1 Bank Address  
Bank Address 0  
1B  
BA0 Bank Address  
w
Address Bus  
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration  
0B  
A13 Address bit 13  
Qoff  
12  
w
w
w
w
Output Disable  
0B  
1B  
QOff Output buffers enabled  
QOff Output buffers disabled  
RDQS  
DQS  
OCD  
11  
Read Data Strobe Output (RDQS, RDQS)  
0B  
1B  
RDQS Disable  
RDQS Enable  
10  
Complement Data Strobe (DQS Output)  
0B  
1B  
DQS Enable  
DQS Disable  
[9:7]  
Off-Chip Driver Calibration Program  
000B OCD OCD calibration mode exit, maintain setting  
001B OCD Drive (1)  
Program  
010B OCD Drive (0)  
100B OCD Adjust mode  
111B OCD OCD calibration default  
AL  
[5:3]  
w
Additive Latency  
Note: All other bit combinations are illegal.  
000B AL 0  
001B AL 1  
010B AL 2  
011B AL 3  
100B AL 4  
Rev. 1.50, 2007-12  
20  
03062006-7M17-PXBC  
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