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HYB18T256400AFL-3.7 参数 Datasheet PDF下载

HYB18T256400AFL-3.7图片预览
型号: HYB18T256400AFL-3.7
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 63 页 / 3597 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T256[40/80/16]0A[C/F](L)  
256-Mbit Double-Data-Rate-Two SDRAM  
FIGURE 2  
Chip Configuration for ×8 components, TFBGA-60 (top view)  
$
9''  
966  
9664  
9''4  
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9664  
9664  
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Notes  
1. RDQS / RDQS are enabled by EMRS(1) command.  
2. If RDQS / RDQS is enabled, the DM function is disabled  
3. When enabled, RDQS & RDQS are used as strobe signals during reads.  
4. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ  
are isolated on the device.  
5. Ball position L8 is Not Connected on 256-Mbit.  
Rev. 1.50, 2007-12  
12  
03062006-7M17-PXBC  
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