Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
2.3
Addressing
This chapter describes the DDR2 addressing.
TABLE 10
256 Mb DDR2 Addressing
Configuration
64 Mb x 41)
32 Mb x 82)
16 Mb x163)
Note
Bank Address
Number of Banks
Auto Precharge
Row Address
BA[1:0]
4
BA[1:0]
4
BA[1:0]
4
A10 / AP
A[12:0]
A11, A[9:0]
A10 / AP
A[12:0]
A[9:0]
10
A10 / AP
A[12:0]
A[8:0]
9
Column Address
4)
5)
Number of Column Address Bits 11
Number of I/Os
4
8
16
Page Size [Bytes]
1024 (1 K)
1024 (1 K)
1024 (1 K)
1) Referred to as ’org’
2) Referred to as ’org’
3) Referred to as ’org’
4) Referred to as ’colbits’
5) PageSize = 2colbits × org/8 [Bytes]
Rev. 1.50, 2007-12
17
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
