Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
2.2
Configuration for TFBGA-84
The chip configuration of a DDR2 SDRAM is listed by function in Table 7. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 8 and Table 9 respectively.
TABLE 7
Configuration
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×16 Organization
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×16 Organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS
Chip Select
Address Signals ×16 Organization
L2
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
L3
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
P7
R2
Rev. 1.50, 2007-12
13
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
