Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
Test Mode
TM
7
w
0B
1B
TM Normal Mode
TM Vendor specific test mode
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
011B CL 3
100B CL 4
101B CL 5
110B CL 6
111B CL 7
BT
BL
3
w
w
Burst Type
0B
1B
BT Sequential
BT Interleaved
[2:0]
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN
.
Rev. 1.50, 2007-12
19
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
