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6
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6
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5()ꢀ
6
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6
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration for ×4 components, TFBGA-60 (top view)
ꢃꢀ
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+ꢀ
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ꢋꢀ
ꢈꢀ
9ꢀ
9ꢀ 6ꢀ
9ꢀ
9ꢀ
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9ꢀ 64
9ꢀ
664ꢀ
1&ꢀ
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9ꢀ 64
9ꢀ
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66ꢀ
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Notes
1. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ
are isolated on the device.
2. Ball position L8 is Not Connected on 256-Mbit
Rev. 1.50, 2007-12
11
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
