HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Currents Specifications and Conditions
Table 31
IDD Measurement Conditions
Parameter
Symbol Note
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are
floating, Data bus inputs are floating.
7)
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD)
;
t
CK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH
between valid commands. Address bus inputs are stable during deselects; Data bus is
switching.
2. Timing pattern for x4 and x8 components:
DDR2-400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
(16 clocks)
DDR2-533: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
(20 clocks)
Timing pattern for x16 components:
DDR2-400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
(20 clocks)
DDR2-533: A0 RA0 A1 RA1 A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D
A7 RA7 D D D (26 clocks)
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized.
3) IDD parameter are specified with ODT disabled.
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for IDD: see Table 32
6) Timing parameter minimum and maximum values for IDD current measurements are defined in Table 46.
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Table 32
Parameter
LOW
Definition for IDD
Description
defined as VIN ≤ VIL(ac).MAX
HIGH
defined as VIN ≥ VIH(ac).MIN
STABLE
FLOATING
SWITCHING
defined as inputs are stable at a HIGH or LOW level
defined as inputs are VREF = VDDQ / 2
defined as: Inputs are changing between high and low every other clock (once per two clocks)
for address and control signals, and inputs changing between high and low every other data
transfer(once per clock) for DQ signals not including mask or strobes
Internet Data Sheet
33
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
