HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Operating Conditions
Table 27
OCD Default Characteristics
Symbol Description
Min.
Nominal
Max.
Unit
Note
1)2)
—
—
—
Output Impedance
—
Ohms
Ohms
Ohms
3)
4)
Pull-up / Pull down mismatch
0
0
—
—
4
Output Impedance step size
for OCD calibration
1.5
5)6)7)8)
SOUT
Output Slew Rate
1.5
—
5.0
V / ns
1) Absolute Specifications (TOPER; VDD = 1.8 V ± 0.1 V; VDDQ = 1.8 V ± 0.1 V), altering OCD from default state no longer
requires DRAM to meet timing, voltage and slew rate specifications on I/O’s.
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV;
(VOUT–VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance
measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms
for values of VOUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and
represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is
18 ± 0.75 Ohms under nominal conditions.
5) Slew Rates according to VIL(ac) to VIH(ac) with the load specified in Figure 72.
6) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured
from AC to AC. This is verified by design and characterization but not subject to production test.
7) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and
t
QHS specification.
8) DRAM output Slew Rate specification applies to 400 and 533 speed bins.
Input / Output Capacitance
Table 28
Symbol
Input / Output Capacitance
Parameter
DDR2-400 &
DDR-2-533
DDR2-667
Unit
Min.
1.0
—
Max.
Min.
1.0
—
Max.
CCK
CDCK
CI
Input capacitance, CK and CK
2.0
2.0
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
0.25
2.0
0.25
2.0
1.0
—
1.0
—
CDI
CIO
0.25
4.0
0.25
3.5
Input/output capacitance,
2.5
2.5
DQ, DM, DQS, DQS, RDQS, RDQS
CDIO
Input/output capacitance delta,
—
0.5
—
0.5
pF
DQ, DM, DQS, DQS, RDQS, RDQS
Internet Data Sheet
29
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
