HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Currents Specifications and Conditions
6
Currents Specifications and Conditions
For Double-Data-Rate-Two SDRAMs described in this data sheet the maximum IDD values are listed in Table 43.
The measurement conditions for IDD characteristics are listed in Table 43, general timing conditions used are listed
in Table 44. At the end of this chapter the on-die-termination currents are defined.
Table 31
IDD Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)6)
Operating Current - One bank Active - Precharge
CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid
IDD0
t
commands. Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
IDD1
I
OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0,
CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control
inputs are switching; Databus inputs are switching.
Precharge Power-Down Current
IDD2P
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data
bus inputs are floating.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
switching, Data bus inputs are switching.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
stable, Data bus inputs are floating.
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data
bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data
bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH
between valid commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD)
;
t
CK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA.
Operating Current
IDD4W
IDD5B
IDD5D
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD)
;
t
CK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
Burst Refresh Current
t
CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
Distributed Refresh Current
t
CK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
Internet Data Sheet
32
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
