HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Timing Characteristics
7.2
AC Timing Parameters
Table 36
Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)
Min.
–450
2
Max.
+450
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
7)
8)
Auto-Precharge write recovery + precharge tDAL
time
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
tIS + tCK + tIH
—
––
—
ns
ps
ps
DQ and DM input hold time (differential data tDH(base)
strobe)
175
––
DQ and DM input hold time (single ended
data strobe)
tDH1(base)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–400
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+400
—
DQS input low (high) pulse width (write cycle) tDQSL,H
9)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
240
Write command to 1st DQS latching
transition
tDQSS
– 0.25
100
––
+ 0.25
—
tCK
ps
DQ and DM input setup time (differential data tDS(base)
strobe)
DQ and DM input setup time (single ended
data strobe)
t
DS1(base)
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
tDSS
tFAW
0.2
—
tCK
tCK
DQS falling edge to CK setup time (write
cycle)
0.2
—
10)11)
12)12)
13)
Four Activate Window period
37.5
—
—
ns
ns
50
Clock half period
tHP
MIN. (tCL, tCH)
14)
Data-out high-impedance time from CK / CK tHZ
—
tAC.MAX
ps
ps
tCK
Address and control input hold time
tIH(base)
275
0.6
—
Address and control input pulse width
(each input)
tIPW
—
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
200
—
ps
ps
ps
tCK
2 × tAC.MIN
tAC.MIN
2
tAC.MAX
tAC.MAX
—
Internet Data Sheet
37
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
