HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Timing Characteristics
Table 35
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
Speed Grade
DDR2–533C
–3.7
DDR2–400B
–5
Unit
Note
IFX Sort Name
CAS-RCD-RP latencies
Parameter
4–4–4
3–3–3
tCK
—
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
Min.
5
Max.
Min.
5
Max.
1)2)3)4)
Clock Frequency
@ CL = 3
8
8
@ CL = 4
@ CL = 5
tCK
3.75
3.75
45
8
5
8
tCK
8
5
8
5)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
40
55
15
15
70000
—
60
15
—
—
15
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS / DQS, RDQS / RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
Internet Data Sheet
36
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
