HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6.2
Write - Basic Sequence
0
1
2
3
4
5
6
7
8
CLK#
CLK
Com.
Addr.
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
WL = 3
WDQS
DQ
D0
D1
D2
D3
D1
WL = 4
WDQS
DQ
D0
D2
D3
Com.
Addr.
WR
B/C
N/D
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = 3
DQ
D0
D1
D2
D0
D3
D1
WL = 4
WDQS
DQ
D2
D3
Addr.: Address B / C
B / C: Bank / Column address
WR: WRITE
NOP: No Operation
DES: Deselect
D#:
Data to B / C
Write Latency
N/P: NOP or DES
Com.: Command
WL:
Don't Care
Figure 28 Write Basic Sequence
1. Shown with nominal value of tDQSS
.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
3. When NOPs are applied on the command bus, the WDQS and the DQ busses remain stable High.
4. When DESs are applied on the command bus, the status of the WDQS and DQ busses is unknown.
Data Sheet
47
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
