HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6
Writes (WR)
4.6.1
Write - Basic Information
with Autoprecharge can be programmed in the Mode
Register. Choosing high values for WR will prevent the
chip to delay the internal Autoprecharge in order to
meet tRAS(min).
CLK#
CLK
CKE
During WR bursts data will be registered with the edges
of WDQS. The write latency can be programmed during
Extended Mode Register Set. The first valid data is
registered with the first valid rising edge of WDQS
following the WR command. The externally provided
WDQS must switch from HIGH to LOW at the beginning
of the preamble. There is also a postamble requirement
before the WDQS returns to HIGH. The WDQS signal
can only transition when data is applied at the chip input
and during pre- and postambles.
CS#
RAS#
CAS#
WE#
tDQSS is the time between WR command and first valid
rising edge of WDQS. Nominal case is when WDQS
edges are aligned with edges of external CLK.
Minimum and maximum values of tDQSS define early
and late WDQS operation. Any input data will be
ignored before the first valid rising WDQS transition.
tDQSL and tDQSH define the width of low and high phase
of WDQS. The sum of tDQSL and tDQSH has to be tCK.
A2-A7, A9
CA
A0, A1
A10-A11
A8
AP
BA
AP: AutoPrecharge
CA: Column Address
BA: Bank Address
BA0-BA2
Back to back WR commands are possible and produce
a continuous flow of input data. There must be one
NOP cycle between two back to back WR commands.
Don't Care
Figure 26 Write Command
Any WR burst may be followed by a subsequent RD
command. Figure 32 shows the timing requirements
for a WR followed by a RD. A WR may also be followed
by a PRE command to the same bank. tWR has to be
met as shown in Figure 35.
Setup and hold time for incoming DQs and DMs relative
to the WDQS edges are specified as tDS and tDH. DQ
and DM input pulse width for each input is defined as
tDIPW. The input data is masked if the corresponding DM
signal is high.
Write bursts are initiated with a WR command, as
shown in Figure 26. The column and bank addresses
are provided with the WR command, and Auto
Precharge is either enabled or disabled for that access.
The length of the burst initiated with a WR command is
four or eight depending on the mode register setting.
There is no interruption of WR bursts. The two least
significant address bits A0 and A1 are ’Don’t Care’.
For WR commands with Autoprecharge the row being
accessed is precharged tWR/A after the completion of
the burst. If tRAS(min) is violated the begin of the internal
Autoprecharge will be performed one cycle after
tRAS(min) is met. WR, the write recovery time for write
All timing parameters are defined with graphics DRAM
terminations on.
Table 20
WDQS
WDQS0
WDQS1
WDQS2
WDQS3
Mapping of WDQS and DM Signals
Data mask signal
Controlled DQs
DQ0 - DQ7
DQ8 - DQ15
DQ16 - DQ23
DQ24 - DQ31
DM0
DM1
DM2
DM3
Data Sheet
45
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
