HYB18H512321AF
512-Mbit GDDR3
Functional Description
CLK#
CLK
tDQSS
tWPRE
nominal WDQS
tDQSH
tDQSL
tDQSH
tWPST
tDS tDH
tDS tDH
Preamble
Postamble
WDQS
DQ
tDIPW
D0
D1
D2
D3
tDS
tDH
DMx
tDIPW
Data masked
Data masked
min(tDQSS
)
early WDQS
WDQS
max(tDQSS
)
late WDQS
WDQS
Don't Care
DMx: Represents one DM line
Figure 27 Basic Write Burst / DM Timing
Note:WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
46
Rev. 1.73, 2005-08
05122004-B1L1-JEN8