HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.5
Bank / Row Activation (ACT)
Before a READ or WRITE command can be issued to
a bank, a row in that bank must be opened.
This is accomplished via the ACT command, which
selects both the bank and the row to be activated.
CLK#
CLK
CKE
After opening a row by issuing an ACT command, a
READ or WRITE command may be issued after tRCD to
that row.
CS#
A subsequent ACT command to a different row in the
same bank can only be issued after the previous active
row has been closed (precharged). The minimum time
interval between successive ACT commands to the
same bank is defined by tRC.
RAS#
CAS#
A subsequent ACT command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACT
WE#
A0-A11
commands to different banks is defined by tRRD
.
RA
BA
There is a minimum time tRAS between opening and
RA: Row Address
BA: Bank Address
closing a row.
BA0-BA2
Don't Care
Figure 22 Activating a specific row
CLK#
CLK
Com.
ACT
R/W
PRE
ACT
ACT
Row: Row Address
A0-A11
Row
B.Y
Col
B.Y
A8
Row
B.Y
Row
B.X
Col: Column Address
B.X: Bank X
B.Y: Bank Y
BA0-BA2
B.Y
R/W: READ or WRITE command
PRE: PRECHARGE command
ACT: ACTIVATE command
tRCD
tRAS
tRC
tRRD
Don't Care
Figure 23 Bank Activating Timing
For eight bank GDDR3 devices, there may be a need to limit the number of activates in a rolling window to ensure
that the instantaneous current supplying capability of the devices is not exceeded. To reflect the true capability of
the DRAM instantaneous current supply, the parameter tFAW (four activate window) is defined. No more than 4
banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and
rounding up the next integer value. As an example of the rolling window, if (tFAW / tCK) rounds up to 10 clocks, and
an activate command is issued in clock n, no more than three further activate commands may be issued in clocks
n+1 through n+9.
Data Sheet
43
Rev. 1.73, 2005-08
05122004-B1L1-JEN8