HYB18H512321AF
512-Mbit GDDR3
Pin Configuration
Table 5
Command Description
SREFEX
Description of Commands
The SREFEX command is used to exit the Self Refresh mode. The DLL is automatically enabled
and resetted upon exiting. The procedure for exiting Self Refresh requires a sequence of
commands. First CLK and CLK must be stable prior to CKE going from LOW to HIGH. Once CKE
is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXSNR is
satisfied. This time is required for the completion of any internal refresh in progress. A simple
algorithm for meeting both refresh, DLL requirements and output calibration is to apply NOPs for
1000 cycles before applying any other command to allow the DLL to lock and the output drivers to
recalibrate.
PWDNEN The PWDNEN command enables the power down mode. It is entered when CKE is set low together
with a NOP/DESEL. The CKE signal is sampled at the rising edge of the clock. Once the power
down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power
consumption. The DLL remains active (unless disabled before with EMRS). All banks can be set to
idle state or stay active. During Power Down Mode, refresh operations cannot be performed;
therefore the refresh conditions of the chip have to be considered and if necessary Power Down
state has to be left to perform an Auto Refresh cycle. If two GDDR3 Graphics RAMs share the same
Command and Address bus, Power down may be entered only for the two devices at the same time.
PWDNEX
A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode.
Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXPN
is satisfied. After tXPN any command can be issued, but it has to comply with the state in which the
power down mode was entered.
DTERDIS
Data Termination Disable (Bus snooping for RD commands) : The Data Termination Disable
Command is detected by the device by snooping the bus for RD commands excluding CS. The
GDDR3 Graphics RAM will disable its Data terminators when a RD command is detected. The
terminators are disabled starting at CL - 1 clocks after the RD command is detected and the duration
is 4 clocks. In a two rank system, both DRAM devices will snoop the bus for RD commands to either
device and both will disable their terminators if a RD command is detected. The command and
address terminators are always enabled. See Figure 14 for an example of when the data
terminators are disabled during a RD command.
Table 6
Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent
Autoprecharge
From Command
To Command
Minimum delay to another bank
(with concurrent autoprecharge)
Note
WR/A
RD or RD/A
WR or WR/A
PRE
(WL + 2) × tCK + tWTR
2 × tCK
tCK
ACT
tCK
RD/A
RD or RD/A
WR or WR/A
PRE
2 × tCK
(CL + 4 - WL) × tCK
tCK
tCK
ACT
Data Sheet
19
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
