HYB18H512321AF
512-Mbit GDDR3
Pin Configuration
Table 5
Description of Commands
Command Description
WR/A
The WR/A command is used to initiate a burst write access to an active row. The value on the BA0,
BA1 and BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the
column location. The value on input A8 is set HIGH. The row being accessed will be precharged at
the end of the write burst. The same individual-bank precharge function is performed which is
described for the PRE command. Auto precharge ensures that the precharge is initiated at the
earliest valid stage within the burst. The user is not allowed to issue a new ACT to the same bank
until the precharge time (tRP) is completed. This time is determined as if an explicit PRE command
was issued at the earliest possible time as described in section “Writes (WR)” on Page 45.
Input data appearing on the DQs is written to the memory array depending on the DM input logic
level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding
data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a write will not be executed to that byte / column location.
PRE
The PRE command is used to deactivate the open row in a particular bank. The bank will be
available for a subsequent row access a specified time (tRP) after the PRE command is issued.
Inputs BA0 - BA2 select the bank to be precharged. A8/AP is set to LOW. Once a bank has been
precharged, it is in the idle state and must be activated again prior to any RD or WR commands
being issued to that bank. A PRE command will be treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging.
PREALL
AREF
The PREALL command is used to deactivate all open rows in the memory device. The banks will be
available for a subsequent row access a specified time (tRP) after the PREALL command is issued.
Once the banks have been precharged, they are in the idle state and must be activated prior to any
read or write commands being issued. The PREALL command will be treated as a NOP for those
banks where there is no open row, or if a previously open row is already in the process of
precharging. PREALL is issued by a PRE command with A8/AP set to HIGH.
The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory
content. The refresh addressing is generated by the internal refresh controller. This makes the
address bits “Don’t Care” during an AREF command. The HYB18H512321AF requires AREF cycles
at an average periodic interval of tREFI(max). To improve efficiency a maximum number of eight
AREF commands can be posted to one memory device (with tRFC from AREF to AREF) as described
in section “Auto Refresh Command (AREF)” on Page 70. This means that the maximum absolute
interval between any AREF command is 8 x tREFI(max). This maximum absolute interval is to allow
the GDDR3 Graphics RAM output drivers and internal terminators to recalibrate, compensating for
voltage and temperature changes. All banks must be in the idle state before issuing the AREF
command. They will be simultaneously refreshed and return to the idle state after AREF is
completed. tRFC is the minimum required time between an AREF command and a following
ACT/AREF command.
SREFEN
The Self Refresh function can be used to retain data in the GDDR3 Graphics RAM even if the rest
of the system is powered down. When entering the Self Refresh mode by issuing the SREFEN
command, the GDDR3 Graphics RAM retains data without external clocking. The SREFEN
command is initiated like an AREF command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering Self Refresh mode and automatically enabled and reset upon
exiting Self Refresh. (1000 cycles must then occur before a RD command can be issued) The active
terminations remain enabled during Self Refresh. Input signals except CKE are “Don’t Care”. If two
GDDR3 Graphics RAMs share the same Command and Address bus, Self Refresh may be entered
only for the two devices at the same time.
Data Sheet
18
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
