HYB18H512321AF
512-Mbit GDDR3
Pin Configuration
13) AUTO REFRESH starts with issuing the command and ends after tRFC
14) Actions MODE REGISTER SET and EXTENDED MODE REGISTER SET start with issuing the command and ends after tMRD
15) Action POWER DOWN EXIT starts with issuing the command and ends after tXPN
16) Action SELF REFRESH EXIT starts with issuing the command and ends after tXSC
.
.
.
.
2.6
Function Truth Table for CKE
Table 8
Function Truth Table II (CKE Table)
CKE
n-1
CKE
n
CURRENT STATE
COMMAND
ACTION
L
L
H
L
H
L
Power Down
Self Refresh
Power Down
Self Refresh
All Banks Idle
Bank(s) Active
All Banks Idle
X
X
stay in Power Down
stay in Self Refresh
Exit Power Down
DESEL or NOP
DESEL or NOP
DESEL or NOP
DESEL or NOP
Auto Refresh
Exit Self Refresh 5
Entry Precharge Power Down
Entry Active Power Down
Entry Self Refresh
Note:
1. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the GDDR3 Graphics RAM immediatly prior to clock edge n.
3. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND.
4. All states and sequences not shown are illegal or reserved.
5. DESEL or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum
of 1000 clock cycles is required before applying any other valid command.
Data Sheet
22
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
