HYB18H512321AF
512-Mbit GDDR3
Pin Configuration
2.3
Functional Block Diagram
A0-A7,A9, A8/AP, A10-A11
BA0-BA2
Address buffer
A8/AP
Row Addresses A0-A11, BA0-BA2
Row Address Buffer
Column Addresses A2-A7,A9
Column Address Buffer
Refresh
Counter
CS
RAS
CAS
WE
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Memory
Bank 4
Memory
Bank 5
Memory
Bank 6
Memory
Bank 7
RES
MF
Memory
Bank 0
Array
Memory
Bank 1
Array
Memory
Bank 2
Array
Memory
Bank 3
Array
Bank 0
Bank 1
Bank 2
Bank 3
4096 x 512
4096 x 512
4096 x 512
4096 x 512
x 32 bit
x 32 bit
x 32 bit
x 32 bit
4096 x 512
x 32 bit
4096 x 512
x 32 bit
4096 x 512
x 32 bit
4096 x 512
x 32 bit
ZQ
CKE
CLK
CLK
DLL
Output Buffers
Input Buffers
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
Figure 2
Functional Block Diagram
Data Sheet
15
Rev. 1.73, 2005-08
05122004-B1L1-JEN8