HYB18H512321AF
512-Mbit GDDR3
Pin Configuration
2.5
State Diagram and Truth Tables
2.5.1
State Diagram for One Activated Bank
The following diagram shows all possible states and transitions for one activated bank. The other 7 banks of the
Graphics SDRAM are assumed to be in idle state.
single bank
WR
RD
ACTIVE
ACT
PRE
WR/A
RD/A
PDEN
PDEX
MRS
EMRS
PDEN
PDEX
active
IDLE
AUTO
POWER DOWN
REFRESH
precharge
SREX
SREN
SELF
REFRESH
all banks
Figure 3
State diagram for one bank
Note:MRS, EMRS, AUTO REFRESH, SELF REFRESH and precharge POWER DOWN are only allowed if all
8 banks are idle.
Data Sheet
20
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
