HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.7.4
Bursts with Gaps
0
1
2
3
6
7
8
9
10
11
12
CLK#
CLK
Com.
Addr.
RD
N/D
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B/Cx
B/Cy
CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
CAS latency = 8
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2
B / Cx: Bank / Column address x
B / Cy: Bank / Column address y
Don't Care
DQs : Terminations off
RDQS : Not driven
RD:
Dx#:
Dy#:
READ
Data from B / Cx
Data from B / Cy
Com.: Command
Addr.: Address B / C
Figure 40 Consecutive Read Bursts with Gaps
1. The second RD command may be either for the same bank or another bank.
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS.
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data.
Data Sheet
59
Rev. 1.73, 2005-08
05122004-B1L1-JEN8