Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
TABLE 7
ON/OFF mode of DQ/DM receivers
WL
DQ/DM-Receivers
3-4
Receivers are always on
5-6-7
Receivers are off and will be switched on by Write command and will be switched off again after
WL+BL
The ON/OFF state of the DQ/DM receivers depends on the Write Latency. The dependence is given in Table 7.
3.1.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and
A8-A11 set to the desired value.
3.1.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits A0-A7 and
A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and
bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of
operations once the DLL reset is completed.
Rev. 1.3, 2007-12
15
05292007-WAU2-UU95
QIMONDA [ QIMONDA AG ]
