Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
3.2.5
Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set to 1 and bits
A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3 DRAM will provide the
Qimonda vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will be driven onto the DQ bus after
tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and Revision ID will be driven on DQ[7:0] until a
new EMRS command is issued with A10 set back to 0. After tRDoff following the second EMRS command, the data bus is driven
back to HIGH. This second EMRS command must be issued before initiating any subsequent operation. Violating this
requirement will result in unspecified operation.
TABLE 8
Revision ID and Vendor Code
Revision Identification
Qimonda Vendor Code
DQ[7:4]
0011
DQ[3:0]
0010
Note: Please refer to Revision Release Note for Revision ID value.
FIGURE 10
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
EMRS
Add
EMRS
Add
Com.
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
A[9:0],
A11
A10
t
t
RIDon
RIDoff
RDQS
DQ[7:0]
Vendor Code and Revision ID
EMRS: Extended Mode Register Set Command
Add:
N/D:
Address
NOP or Deselect
Don't Care
Rev. 1.3, 2007-12
19
05292007-WAU2-UU95
QIMONDA [ QIMONDA AG ]
