RM7965A-900UI 参数 Datasheet PDF下载

型号：	RM7965A-900UI
PDF下载：	下载PDF文件查看货源
内容描述：	[Microprocessor, 64-Bit, 900MHz, CMOS, PBGA256, 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256]
分类和应用：	时钟外围集成电路
文件页数/大小：	74 页 / 508 K
品牌：	PMC [ PMC-SIERRA, INC ]

RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet

List of Tables

Table 1 Acronyms and Abbreviations........................................................................................10

Table 2 Instruction Issue Rules................................................................................................. 15

Table 3 Dual Issue Instruction Classes..................................................................................... 16

Table 4 Integer ALU Operations................................................................................................ 19

Table 5 Integer Multiply/Divide Operations ............................................................................... 19

Table 6 Floating Point Latencies and Repeat Rates................................................................. 21

Table 7 Kernel Mode Virtual Addressing (32-bit) ...................................................................... 24

Table 8 Cause Register............................................................................................................. 26

Table 9 Interrupt Control Register............................................................................................. 27

Table 10 IPLLO Register........................................................................................................... 27

Table 11 IPLHI Register............................................................................................................ 27

Table 12 Interrupt Vector Spacing............................................................................................. 28

Table 13 E9000 Cache Operating Modes................................................................................. 34

Table 14 RM7965A Cache Attributes........................................................................................35

Table 15 Cache Locking Control...............................................................................................36

Table 16 On-Chip Memory Latencies........................................................................................37

Table 17 Watch Registers......................................................................................................... 45

Table 18 Performance Counter Control .................................................................................... 46

Table 19 System Interface ........................................................................................................ 55

Table 20 Clock/Control Interface............................................................................................... 56

Table 21 Power Supply ............................................................................................................. 56

Table 22 Interrupt Interface....................................................................................................... 57

Table 23 JTAG Interface ........................................................................................................... 57

Table 24 Initialization Interface.................................................................................................. 57

Table 25 (VccIO = 3.15 V – 3.45 V) .......................................................................................... 60

Table 26 (VccIO = 2.3 V – 2.7 V) .............................................................................................. 60

Table 27 (VccIO = 1.4 V – 1.6 V) HSTL.................................................................................... 60

Table 28 Normal Operating Voltages for 0.13 μm CMOS.........................................................61

Table 29 VccINT Power Requirements.....................................................................................62

Table 30 Conditions for Power Requirements .......................................................................... 62

Table 31 Device Compact Model²............................................................................................. 67

Table 32 Heat Sink Requirements .............................................................................................67

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

Document No.: PMC-2100294, Issue 2