RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
1
Definitions
Table 1 defines the abbreviations used in this data sheet.
Table 1 Acronyms and Abbreviations
Acronym or Abbreviation
Description
CPU
Central Processing Unit
CPLD
DDR
Complex Programmable Logic Device
Double Data Rate
DMA
Direct Memory Access
ECC
Error Correction Code
EJTAG
FCRAM
FPGA
I/O
Enhanced Joint Test Action Group
Fast Cycle RAM
Field-programmable Gate Array
Input/Output
LVTTL
MIPS
Low-voltage Transistor-Transistor Logic
Millions of Instructions Per Second
Microprocessor without Interlocked Pipeline Stages
Memory Management Unit
5-State Algorithm for Cache Coherency:
Modified/Owned (Modified-Shared)/Exclusive/ Shared/Invalid
Non-maskable Interrupt
MMU
MOESI
NMI
PAL
Programmed Array Logic
PLL
Phase Lock Loop
RAM
ROM
SDRAM
SMP
SSTL
SysAD
TAP
Random Access Memory
Read-only Memory
Synchronous Dynamic RAM
Symmetric Multi-processing
Stub Series Terminated Logic
Multiplexed Address/Data System Bus
Test Access Port
TLB
Translation Lookaside Buffer
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
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PMC [ PMC-SIERRA, INC ]
