RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Table of Contents
Legal Information........................................................................................................................... 2
Copyright................................................................................................................................. 2
Disclaimer ............................................................................................................................... 2
Trademarks............................................................................................................................. 2
Patents.................................................................................................................................... 2
Revision History............................................................................................................................. 4
List of Figures................................................................................................................................ 8
List of Tables.................................................................................................................................. 9
1
2
Definitions ............................................................................................................................. 10
Introduction ........................................................................................................................... 11
2.1 Features ...................................................................................................................... 11
Block Diagram....................................................................................................................... 13
E9000 CPU Core .................................................................................................................. 14
4.1 CPU Registers.............................................................................................................14
4.2 Superscalar Dispatch..................................................................................................15
4.3 Seven-stage Pipeline .................................................................................................. 16
4.3.1 RM7000 Pipeline Stages................................................................................ 16
4.3.2 E9000 Pipeline Stages................................................................................... 17
4.4 Delay slots................................................................................................................... 18
4.4.1 Branch Delay.................................................................................................. 18
4.4.2 Load Delay.....................................................................................................18
4.5 Branch Prediction........................................................................................................18
4.6 Integer Unit.................................................................................................................. 18
4.6.1 Register File................................................................................................... 19
4.7 Integer ALU ................................................................................................................. 19
4.8 Integer Multiply/Divide................................................................................................. 19
4.9 Floating-Point Coprocessor......................................................................................... 20
4.10 Floating-Point Unit.......................................................................................................20
4.11 Floating-Point General Register File...........................................................................22
4.12 System Control Coprocessor (CP0)............................................................................ 22
4.13 System Control Coprocessor Registers...................................................................... 22
4.14 Memory Management Unit (MMU).............................................................................. 23
4.15 Virtual to Physical Address Mapping........................................................................... 24
4.16 Joint TLB ….................................................................................................................25
3
4
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
5
PMC [ PMC-SIERRA, INC ]
