RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Pin Name
Type
Description
SysAD[63:0]
Input/Output
System address/data bus
A 64-bit address and data bus for communication between the
processor and an external agent.
SysADC[7:0]
SysCmd[8:0]
SysCmdP
Input/Output
Input/Output
Input/Output
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during
data cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between
the processor and an external agent.
System Command/Data Identifier Bus Parity
For the RM7965A, unused on input and zero on output.
Table 20 Clock/Control Interface
Pin Name
SysClock
Type
Description
Input
System clock
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor
selected during boot initialization.
SysClock*
Input
System clock
Differential clock input used only in HSTL I/O mode. Set SysClock*
to VccIO or Do Not Connect for non-HSTL operation.
Table 21 Power Supply
Pin Name
VccInt
Type
Input
Input
Input
Description
Power supply for core.
Power supply for I/O.
Vcc for PLL
VccIO
VccP
Quiet VccInt for the internal phase locked loop. Must be connected
to VccInt through a filter circuit.
VccJ
Vref_In
Vss
Input
Input
Input
Input
Power supply used for JTAG.
Reference voltage for HSTL I/O. Do Not Connect for non-HSTL.
Ground Return.
VssP
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to
Vss through a filter circuit.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
56
PMC [ PMC-SIERRA, INC ]
