RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Pin Name
Reset*
Type
Description
Input
Reset
This signal must be asserted for any reset sequence. It may be
asserted synchronously or asynchronously for a cold reset, or
synchronously to initiate a warm reset. Reset must be de-asserted
synchronously with SysClock.
ModeClock
Output
Boot Mode Clock1
Serial boot-mode data clock output at the system clock frequency
divided by two hundred and fifty six.
ModeIn
Input
Input
Boot Mode Data In
Serial boot-mode data input.
HSTL/LVTTL Control
HSTL_Sel*
Asserting this signal low places the system I/O pins in HSTL mode.
Pulling this signal high or allowing to float places all system I/O pins
in LVTLL mode.
Note
1. In HSTL mode, maximum voltage level of the ModeClock is determined by VccJ.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
58
PMC [ PMC-SIERRA, INC ]
