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RM7965A-900UI 参数 Datasheet PDF下载

RM7965A-900UI图片预览
型号: RM7965A-900UI
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor, 64-Bit, 900MHz, CMOS, PBGA256, 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 508 K
品牌: PMC [ PMC-SIERRA, INC ]
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RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet  
Table 22 Interrupt Interface  
Pin Name  
INT[9:0]*  
Type  
Description  
Interrupt  
Input  
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the  
interrupt register.  
Non-maskable interrupt  
NMI*  
Input  
Non-maskable interrupt, ORed with bit 15 of the interrupt register..  
Table 23 JTAG Interface  
Pin Name  
JTDI/DBDI  
Type  
Description  
JTAG/EJTAG data in  
Input  
JTAG/EJTAG serial data in.  
JTAG/EJTAG clock input  
JTAG/EJTAG serial clock input.  
JTAG/EJTAG data out  
JTAG/EJTAG serial data out.  
JTAG/EJTAG command  
JTCK/DBCK  
JTDO/DBDO  
Input  
Output  
JTMS/DBMS  
Input  
JTAG/EJTAG command signal, signals that the incoming serial data  
is command data.  
JTRST*/DBRST* Input  
JTAG/EJTAG reset.  
JTAG/EJTAG select  
JTAGSEL  
Input  
Selects JTAG when JTAGSEL=1 ; selects EJTAG when JTAGSEL=0  
Notes:  
1. The JTRST* input was added to the RM70xxC and RM7965A CPUs to directly control the reset to the  
JTAG state machine. JTAG boundary scan test equipment must be able to drive JTRST* high to allow  
JTAG boundary scan operation.  
2. The JTRST* input must be connected to GND (Vss) through a 220 to 1 Kpull-down resistor to  
force the JTAG state machine into the reset state to allow normal operation (JTAG boundary scan  
mode disabled).  
3. The JTAG interface electrical characteristics are dependent on the VccJ level chosen (2.5 V or 3.3 V).  
Table 24 Initialization Interface  
Pin Name  
BigEndian  
Type  
Description  
Input  
Big Endian / Little Endian Control  
Allows the system to change the processor addressing mode without  
rewriting the mode ROM.  
VccOK  
Input  
Input  
Vcc is OK  
When asserted, this signal indicates to the RM7965A that the VccInt  
power supply has been above the recommended value for more than  
100 milliseconds and will remain stable. The assertion of VccOK  
initiates the reading of the boot-time mode control serial stream.  
ColdReset*  
Cold Reset  
This signal must be asserted for a power on reset or a cold reset.  
ColdReset must be de-asserted synchronously with SysClock.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2100294, Issue 2  
57  
 
 
 
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