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RM7965A-900UI 参数 Datasheet PDF下载

RM7965A-900UI图片预览
型号: RM7965A-900UI
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor, 64-Bit, 900MHz, CMOS, PBGA256, 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 508 K
品牌: PMC [ PMC-SIERRA, INC ]
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RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet  
9
RM7000 and RM7965A Differences  
Feature  
RM7000  
RM7965A  
Number of CPU Cores  
Pipeline Stages  
1
1
5
7
Load Delay, Branch Delay  
Branch Prediction  
1
2
No  
No  
Parity  
8K BHT/Core  
No  
Hardware Cache Coherency Support  
Secondary Cache Protection  
Error Checking and Correcting  
(ECC)  
Page Size  
4 KB – 16 MB  
4 KB – 256 MB  
12  
Number of ASID Bits  
New Instructions  
8
MSUB, MSUBU, SSNOP,  
SDBBP, DERET  
Integer Multiplier  
Integrated Buses  
SysAD Bus Width  
Iterative  
SysAD  
Pipelined  
SysAD  
64-bit  
64-bit (RM7000x), RM7065x) or  
32-bit (RM7035C)  
SysAD Maximum Bus Frequency  
125 MHz (RM70xxA)  
133 MHz (LVTTL) or 200 MHz  
(HSTL)  
133 MHz (LVTTL) or 200 MHz  
(HSTL) for all RM70xxC CPUs  
L3 Cache Interface  
Yes (RM7000x only)  
No  
L3 Page Invalidate Cache Op  
On-Chip Debugging  
Stores TagLo register  
Stores constant zero  
No  
Yes  
Yes  
Yes  
Virtual  
2
EJTAG Emulator Support  
Integrated Instruction Trace Buffer  
Watch Register Addressing  
Number of Performance Counters  
No  
No  
Physical  
1
The following lists the significant additions to the RM7965A product:  
The SysAD bus supports both 133 MHz LVTTL and 200 MHz HSTL SysAD bus  
frequencies.  
Integrated debug support includes EJTAG TAP support and on-chip trace buffers. The  
added debug mechanism includes two new instructions: Software Debug Break Point  
(SDBBP), and Debug Exception Return (DERET). The added debug mechanism has its own  
exception vector located at 0xBFC00480 and its own 2 MB memory space at 0xFF200000.  
New instructions: Multiply-Subtract, both signed and unsigned (MSUB/MSUBU), and  
superscalar NOP (SSNOP) which issues a NOP to each pipeline.  
Branch prediction that provides the CPU core with up to 8K entries of branch history.  
Virtual Watch register addressing. This is a change from the physical Watch register  
addressing on the RM7000. The two Watch registers and the Watch Mask have been  
enlarged to reflect this change.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2100294, Issue 2  
53  
 
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