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RM7965A-900UI 参数 Datasheet PDF下载

RM7965A-900UI图片预览
型号: RM7965A-900UI
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor, 64-Bit, 900MHz, CMOS, PBGA256, 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CSBGA-256]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 508 K
品牌: PMC [ PMC-SIERRA, INC ]
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RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet  
10 Pin Descriptions  
The following is a list of control, data, clock, tertiary cache, interrupt, and miscellaneous pins of  
the RM7965A.  
Table 19 System Interface  
Pin Name  
ExtRqst*  
Type  
Description  
Input  
External request  
Signals that the external agent is submitting an external request.  
Release interface  
Release*  
Output  
Signals that the processor is releasing the system interface to slave  
state  
RdRdy*  
WrRdy*  
Input  
Input  
Read Ready  
Signals that an external agent can now accept a processor read.  
Write Ready  
Signals that an external agent can now accept a processor write  
request.  
ValidIn*  
Input  
Valid Input  
Signals that an external agent is now driving a valid address or data  
on the bus and a valid command or data identifier on the SysCmd  
bus.  
ValidOut*  
Output  
Valid output  
Signals that the processor is now driving a valid address or data on  
the SysAD bus and a valid command or data identifier on the  
SysCmd bus.  
PRqst*  
Output  
Input  
Processor Request  
When asserted this signal requests that control of the system  
interface be returned to the processor.  
PAck*  
Processor Acknowledge  
When asserted, in response to PRqst*, this signal indicates to the  
processor that it has been granted control of the system interface.  
RspSwap*  
Input  
Response Swap  
RspSwap* is used by the external agent to signal the processor  
when it is about to return a memory reference out of order; i.e., of two  
outstanding memory references, the data for the second reference is  
being returned ahead of the data for the first reference. In order that  
the processor will have time to switch the address to the tertiary  
cache, this signal must be asserted a minimum of two cycles prior to  
the data itself being presented. Note that this signal works as a  
toggle; i.e., for each cycle that it is held asserted the order of return is  
reversed. By default, anytime the processor issues a second read it  
is assumed that the reads will be returned in order; i.e., no action is  
required if the reads are indeed returned in order.  
RdType  
Output  
Read Type  
During the address cycle of a read request, RdType indicates  
whether the read request is an instruction read or a data read.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2100294, Issue 2  
55  
 
 
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