Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
1.7.1 The OOB Bus
The OOB bus is an eight-bit, tri-state, multiplexed address/data bus with separate control and interrupt
signals.
1.7.1.1 OOB Bus Signals
Thirteen signals are used:
Table 17. OOB Control Bus Signals
Signal
Name
Description
8 bit address/data bus.
AD[7] indicates the type of cycle (1 = Write, 0 = Read)
during the first address cycle, and is used for for
address/data during other cycles.
Driven by M(aster) or S(lave)
AD[7:0]
Both.
Address driven by master.
Data supplied by master for a
write cycle.
Data supplied by Slave for a
read cycle.
A[6:0] must provide the board select address when
VALID_L is high.
VALID_L
WAIT_L
Bus cycle is valid. Active low.
Master.
Slave
Wait. Active low.
Initially asserted to indicate slave will respond.
Then asserted, if necessary, to allow slave extra cycles
to respond to current transaction.
CLK
Clock.
Clock source.
Slave
INT_HI
INT_LO
High priority interrupt
Low priority interrupt
Slave
NOTE: Active low signals are indicated by “_L”.
All signals are point to point except for the AD bus which is a multipoint bus. In particular,
WAIT_L and the interrupt signals are not open collector/gate drivers.
1.7.1.2 Address Space
The OOB bus provides 31 bits of address - A[30:0]. Of these, bits A[1] and A[0] are always 0 as the bus
does not support 8- or 16-bit accesses: all accesses are 32-bits wide, and must be aligned on quad byte
boundaries.
78
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
