RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Assuming the use of 8b/10b Serdes, then we suggest the following mapping:
Table 73. Suggested 8b/10b Decode Map Within the Dataslice
8b/10b code
Dataslice code
K28.5
Control 0
Control 1 through
254
K27.7
K29.7
Control 255
Figure 92. Initial Sequence Expected at Port Card
K28.5 K27.7 K27.7 K27.7 K27.7 K27.7 K28.5
Linecard
Serdes
Dataslice
The initial control word sequence decoded by the Dataslice is expected to be {0,1,1,1,1,1,0,1,1...}
Once the Dataslice has seen five consecutive occurrences of the expected sequence it then locks its cell
timing so that the K28.5 word corresponds to the first word in the cell.
The linecard may instead send {K28.5, K29.7, K29.7, K29.7, K29.7, K29.7}. This simply tells the Dataslice
that the linecard’s receiver has locked onto the Dataslice’s transmitted signal. This is useful because it tells
the ETT1 CPU that the link is up and locked in both directions.
The transmit side of the Dataslice sends the same sequence: it starts by sending {K28.5, K27.7, K27.7,
K27.7, K27.7, K27.7}. When the receive side of the Dataslice has achieved cell frame lock then the
transmit side changes to send {K28.5, K29.7, K29.7, K29.7, K29.7, K29.7} instead.
The sequence {K28.5, K27.7, K27.7, K27.7, K27.7, K27.7} is called Idle-not-ready.
The sequence {K28.5, K29.7, K29.7, K29.7, K29.7, K29.7} is called Idle-ready.
Table 74 shows the state machine operated by the transmit side of the Dataslice.
Table 74. Dataslice Egress Truth Table
8B/10B Encoder
Output Fifo Status 8B/10B Ingress Link Ready 10B Transmit Data (TxD)
Enable
0
1
1
1
1
don’t care
don’t care
Null (10’b0)
K28.5, K27.7
K28.5, K29.7
Dxx.x
0 (FIFO empty)
0
0
1
1 (FIFO not empty)
1
don’t care
don’t care
Dxx.x
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
331
PMC [ PMC-SIERRA, INC ]
