RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 93. Cells May Be Skewed Between Dataslices
Dataslice x
cell n-1
cell n
max Tx skew
Dataslice y
Dataslice z
cell n
cell n+1
cell n+1
cell n
C.2.2.2
Channel Errors
Each link in the channel can, of course, suffer bit errors as discussed in the section on link errors above.
However, the channel can incur a particular type of error which the system designer must be aware of.
As mentioned above, it is possible for three or more data words in a data cell to be corrupted to look like
control words. The Dataslice decides whether a cell is a data cell or Idle cell based on the majority of words
seen. It is important to understand that each Dataslice decides independently whether a received cell is an
idle cell or a data cell. This decision is based on a majority vote among the six characters received in a cell
time: Kxx.x characters identify idle cells and Dxx.x characters identify data cells. It is very unlikely but
nevertheless possible that a burst of bit errors on the fiber corrupt more than half of the characters in a cell
time in such a way that an idle cell is mistaken for a data cell and vice-versa. Because idle cells are not
written into the input FIFO of the Dataslice this condition causes every subsequent cell to be misaligned as
it is read from the input FIFO and passed on to the port processor.
There are cases where the corruption of control words is recognized by the Dataslice and signalled to the
linecard by dropping the ingress ready status (DIR#9 and revert to sending idle-not-ready cells). In other
cases, this condition is only recognized by the port processor when the LCS header is misaligned and in
that case LCS CRC error interrupts will be raised. If the misalignment occurs in the cell payload, the
linecard must recognize this condition either by checking CRCs on a cell or packet level or by means of a
keep-alive watchdog traffic stream (for example, a loopback TDM connection). The recommended
recovery actions from this rare condition require the port to be taken down and brought back up again.
C.3
MANAGING CELL RATES (SETTING THE IDLE COUNT REGISTER)
To avoid cell loss due to buffer overrun it is necessary that the linecard does not send cells at a rate that
exceeds the ETT1 port cards ability to accept cells. Note: by buffer overrun we refer to the shallow,
rate-matching FIFOs within the various devices; we do not mean the ingress or egress queues. The same
is true for the ETT1 port card: it should not send cells at a rate that will cause cell loss at the linecard.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
335
PMC [ PMC-SIERRA, INC ]
