RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 90. Cells are Striped Across the 12 Physical Links
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1 cell
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The link technology used is the same as that used by Gigabit Ethernet (GE), except that it operates at
1.5 Gbaud (150MHz) instead of 1.25 Gbaud (125MHz). While the Dataslice can be programmed to use
any arbitrary 8b/10b code, the ETT1system has been focused on the use of the GE standard and thus the
8b/10b code developed originally by IBM. The following discussion assumes the use of standard Serdes
components; however an alternative 8b/10b scheme could be used if suitable physical level components
are available.
C.2.1 Link
Before looking at how the channel operates, we first consider a single link in its various aspects: physical
interface, initialization, and errors.
C.2.1.1 Link Physical Interface
Each logical Dataslice device connects to a Serdes device via 10-bit wide transmit and receive interfaces,
operating at 150MHz in a source synchronous mode - i.e. the data is accompanied by a suitable clock. The
Serdes transmits a serialized bit stream to a 1.5Gbaud VCSEL and receives a serialized bit stream from a
1.5Gbaud PIN diode.
The ETT1 port card provides a 150MHz oscillator that is used as a reference clock for the Dataslice
parallel bus transmitters. In the egress direction this reference clock is provided to the Dataslice which
adjusts the phase of the reference so that it is aligned in mid-bit time of the transmitted word. In the ingress
direction the Serdes device recovers a nominal 150MHz receive clock from the incoming serial stream and
provides it to the Dataslice receiver. The Dataslice expects to sample the incoming 10-bit word using the
receive clock; the data is then re-synchronized internally within the Dataslice. Figure 91 illustrates the two
directions.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
329
PMC [ PMC-SIERRA, INC ]
