RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 91. The 10-bit Data Paths
fotx_clk_in (~150MHz)
10 fotx0_txd[]
Serdes Tx
VCSEL
VCSEL
Dataslice Tx
fotx_clk_out (~150MHz)
Serdes Tx
10 fotx1_txd[]
fotx_txd[9:0]
fotx_clk_out
forx0_clk (~150MHz)
Serdes Rx
PIN diode
PIN diode
10 forx0_rxd[]
Dataslice Rx
forx1_clk (~150MHz)
Serdes Rx
10 forx1_rxd[]
forx_rxd[9:0]
forx_clk_in
C.2.1.2
Link Initialization
At power-on, every individual link needs to be initialized so that the receiver can lock onto the incoming
stream and can identify both word and cell boundaries. To this end, the transmitter must send a particular
sequence of 8b/10b control words. Now, the Dataslice assumes that it will be supplied with a word clock
(forx_clk) and so only needs to determine a cell boundary. Remember that each Dataslice only sees six
words of each cell. So the Dataslice looks for one occurrence of control word 0 followed by five
occurrences of some other control word (e.g. 1). The Dataslice has its own 10b->8b decoder and so it can
map an arbitrary 8b/10b control word to its own decoded control word.
330
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
