RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
we need to realign the output from the 12 channels. This re-alignment (or synchronization) is achieved as
follows.
The Dataslices provide a mechanism that guarantees that the slices of the same cell are removed from the
input FIFOs synchronously in the core ETT1 clock domain1. This synchronization is achieved by only
removing cells from the input FIFO when all 12 Dataslices have received their 6 bytes of a given cell. To
accomplish this, upon each new cell arrival, a token is passed from Dataslice 0 to the EPP, which in turn
broadcasts the token back to every Dataslice after an additional programmed token delay. . Refer to
Section 3.4.2.39 “Internal Delay Matching Adjustments” on page 188. Each token that is granted by the
EPP allows for one cell to be removed from the input FIFO of each Dataslice and sent to the EPP.
The token delay mechanism compensates for a certain amount of skew/delay measured from arrival at
Dataslice 0 to arrival at Dataslices 1 through 11. Additional depth in the input FIFO, beyond the depth
required to support the token delay, compensates for skew from arrival at Dataslices 1 through 11 to arrival
at Dataslice 0. Table 75 shows the allowable skew in each direction for each possible value of the
programmed token delay, in units of 150MHz clock cycle times.
Table 75. Programmed Token Delay vs. Inter-link Skew
Max Skew DS0 to DS1 through
11 (150 MHz Clock Cycles)
Max Skew DS1 through 11 to
DS0 (150 MHz Clock Cycles)
Programmed Token Delay
0
1
2
3
11
17
23
29
19
13
7
1
Possible sources of skew include linecard launch timing, fiber, connector, serializer/deserializer, mux chip.
The worst-case skew depends on the system design. Therefore the system designer must determine the
worst-case skew in each direction relative to Dataslice 0, and select a programmed token delay value that
will provide adequate protection against both worst cases. The smallest sufficient token delay should be
chosen, because the programmed token delay adds to the (E)PP/DS contribution to the RTT and
decreases the budget for the rest of the system (see C.1.2).
In the transmit direction from the Dataslice to the linecard there is no synchronization. Each Dataslice
makes its own decision, at every cell time, as to whether or not it has a cell to send. An Idle cell is
transmitted whenever the output FIFOs is empty. The Dataslice egress start-of-cell synchronization is
determined independently by each Dataslice based on the asynchronous reset pulse. Further, the empty to
non-empty transition of the output FIFOs can be skewed by up to one clock cycle in the 150MHz transmit
clock domain. Therefore, it is possible for transmit cells to be skewed by up to one cell time or six 150MHz
transmit clock cycles at the Dataslice egress, as shown in Figure 93. Consequently, the linecard must
resynchronize the incoming slices to form the complete cell.
1. All ETT1 devices operate from the same core clock of 200MHz.
334
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
