Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 46. AIB Control/Status Signals.
Duplex AIB Link
AIB Tx Enable
AIB Reset
OOB Registers
AIB Ready
AIB CRC err
Assuming that the link is connected to an AIB peer, then the first step is to enable the transmitter (AIB_Tx_
Enable) and reset the link (AIB_Reset). The driver is inactive until AIB_Tx_Enable is set to 1, as indicated
in the Figure 46. The link will start to train as soon as reset is deasserted. Assuming that the link trains
correctly then the AIB_Ready signal for this link will be asserted. If the AIB_Ready signal is asserted then
the bidirectional link is operational, so both receivers have trained correctly.
The link will now be operating in normal mode, transmitting data frames. If a transient error corrupts a
frame, causing a CRC mismatch, then the AIB_CRC_err signal will be asserted. If four consecutive frames
encounter CRC errors then the receiver will consider the link to have failed. In this case the training
sequence will be restarted and AIB_Ready signal will be deasserted.
Of course a link might fail, restart and retrain faster than software can respond to an interrupt. In that case
the ETT1 devices have separate OOB registers that indicate whether the AIB_Ready signal has
transitioned. Thus, software can determine which link is having a problem. A failing link will also cause the
AIB_CRC_err bit to be set.
1.10.4 Live Insertion
The AIB drivers should remain disabled until the attached receiver has reached its intended operating
voltage. So do not enable an AIB driver unless the peer AIB receiver is inserted in the system and
operating (i.e. voltage levels are steady). At reset all AIB drivers will be disabled (tri-stated). If the CPU
detects that a board is being withdrawn from the system then it should immediately assert AIB reset for the
link that is not being removed and deassert AIB_Tx_Enable for the AIB drivers at both ends of the link.
1.11 SYSTEM LATENCIES
The ETT1 Chip Set operates in a cell-synchronous mode. Therefore all event latencies described here are
defined in terms of ETT1 cell times (40ns). Further, all events are defined relative to the Dataslice to
linecard interface (Serdes interface).
104
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
