Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
1.11.1 LCS Request to Grant Minimum Latency
This is the minimum latency from when the EPP receives a request from the linecard (1 in Figure 47.) to
when the EPP sends an LCS grant (2). These are relative to the Dataslice interface as shown, not the EPP.
This minimum latency is 16 cell times.
Figure 47. Request to Grant latency
1
Crossbar
Input Data Slice
Output Data Slice
Output EPP
2
Flow Control
Crossbar
Input EPP
Scheduler
1.11.2 LCS Grant to Linecard Cell Latency
This is the maximum latency from when the iEPP issues an LCS grant (1 in Figure 48.) to when the iEPP
expects to receive the cell body associated with the grant (2). These are relative to the Dataslice interface
as shown, not the EPP.
The maximum latency is 42 cell times minus the programmed value of the “DSiFIFO Token Mechanism
Delay” field of the EPP EIDMA register (0009Ch). This is explained in more detail in C.2.2.1
“Synchronization,” on page 333.
,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
105
PMC [ PMC-SIERRA, INC ]
