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PM8621 参数 Datasheet PDF下载

PM8621图片预览
型号: PM8621
PDF下载: 下载PDF文件 查看货源
内容描述: NSE- 8G⑩标准产品数据表初步 [NSE-8G⑩ Standard Product Data Sheet Preliminary]
分类和应用:
文件页数/大小: 184 页 / 957 K
品牌: PMC [ PMC-SIERRA, INC ]
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NSE-8G™ Standard Product Data Sheet  
Preliminary  
°
Triggers a write to offline connection memory page at 0x1000.  
Go to step 1 to begin the mapping change for a new byte in the frame.  
12.6.3 Reading Configurations  
It is possible to read configurations from the offline connection memory page. The following  
example shows this reading operation.  
Example: Suppose one wishes to read which DIN ports map to DOUT[17:12][12:0] for the  
4097th byte of the frame within the offline connection memory page.  
Steps:  
1. CPU writes 0x80081000 to the DCB Access Mode register. (A binary value of 010XX on  
PORTADDR[4:0] indicates to supply the mapping the Configuration Port 17-12 register.)  
2. Wait for six SYSCLK cycles.  
3. CPU reads the mapping from the DCB Configuration Output register.  
Note:  
1. The Access Mode register should NOT be accessed more frequently than once ever 4 SYSCLK cycles  
when initiating write transfers.  
2. When initiating a read from the offline connection memory page to the Configuration Output register,  
there is a latency of 6 SYSCLK cycles from when a read is initiated till when valid data appears on  
CFG_O.  
3. User should perform this operation only when there is no page swap pending (SWAPV = ‘0’) and page  
copy is inactive (UPDATEV = ‘0’).  
12.6.4 DCB Online to Offline Memory Page Copy  
There are two ways in which a connection memory page copy can occur; forced and automatic.  
In forced mode, the CPU initiates a page copy by writing to the DCB Interrupt Status register.  
The page copy begins immediately after being initiated.  
In automatic mode, the AUTO field must be set to logic one. When a connection memory page  
swap occurs, the online connection memory page is copied to the offline connection memory  
page.  
Interrupt generation to signal the page copying status can be enabled to simplify software  
scheduling by setting the UPDATEE field in the DCB Configuration register to logic one. In this  
mode, the UPDATEI field in the DCB Interrupt Status register can be used as the interrupt signal  
to control the microprocessor.  
Alternatively, the microprocessor can poll the UPDATEV field within the DCB Configuration  
register to detect the status of the connection memory page update logic. Logic one indicates  
copying in progress and logic zero indicates copying complete.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-2010850, Issue 1  
146