NSE-8G™ Standard Product Data Sheet
Preliminary
RC1FP (ext)
outgoing
outgoing
messages
messages
1
2
3
4
1
2
3
4
NSE C1FP
(int)
NSE Frame
Interrupt
NSE CPU
tasks
SBS samples new page
bits and set up page
switch
Switch occurs in the SBS
Write new DCB
page bit and
disable Frame
interrupt
Write new SBS
page words
Enable Frame
Interrupt
SBS sample
new bit
DCB sample
new bit
NSE DCB samples CMP
bit and set up page switch
Switch occurs in the NSE
12.5 Controlling Frame Alignment in the Receive Port
After external data corruption on any port it may be necessary to force OCA to reset the
alignment of the R8TD block. In order to detect this out of alignment condition, three hardware
functions are implemented for each port. The registers are:
•
•
•
“Correct R8TD_RX_C1 Pulse Monitor”, 012h
“Unexpected R8TD_RX_C1 Pulse Interrupt”, 013h
“Missing R8TD_RX_C1 Pulse Interrupt”, 014h
These are qualified against a delayed version of the RC1FP input, which should occur every 4 or
48 frames and in agreement with mf_swap mode (DCB Configuration Register, 04Ch). If all
active ports are using carrying the same frequency of C1 frame pulses (1 in 4 or 1 in 48) then the
unexpected interrupt (013h) should be used to signal that a C1 code word was detected at the
wrong time, software can then poll the monitor register (012h) to see if the error condition is
permanent.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
143
PMC [ PMC-SIERRA, INC ]
