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PM8621 参数 Datasheet PDF下载

PM8621图片预览
型号: PM8621
PDF下载: 下载PDF文件 查看货源
内容描述: NSE- 8G⑩标准产品数据表初步 [NSE-8G⑩ Standard Product Data Sheet Preliminary]
分类和应用:
文件页数/大小: 184 页 / 957 K
品牌: PMC [ PMC-SIERRA, INC ]
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NSE-8G™ Standard Product Data Sheet  
Preliminary  
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CMP inputs will be sampled every 48th frame at the internally flywheeled RC1FP  
location.  
If enabled, FRAMEI will occur every 48 frame at the internally flywheeled RC1FP  
location.  
Note: It is vital to ensure that switching of the DS0 bytes containing CAS bits be performed  
correctly through software configuration. That is, these bytes should all be preserved and  
switched to the same output link to preserve the CAS for downstream devices.  
12.11 ILC Operation  
Operating each of the 32 ILC blocks requires the same procedure. Each ILC will be operating  
independently and wait states required for each ILC can be satisfied by interleaving the access  
cycles of several ILC blocks together.  
The ILC is synchronized by the C1 pulse accompanying the input data stream on the  
TelecomBus. It preloads a 9720 counter using this C1 pulse. C1 as shown in Figure 26, will be  
high when the byte in column 25, row 1 is on the input data pins. A 2 bit counter is also kept to  
keep track of the 4-frame multiframe, ie. 4 x 9720 count. This is indicated by C1 being present  
only in the first frame of a multiframe. (could be 1in 4 or higher multiples).  
Figure 26 C1 Position in the First Row  
Column  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25  
Row 1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 C1  
The ILC inserts and retrieves messages from the transport overhead of the SONET/SDH frame on  
the telecom-bus. Figure 27 illustrates the four rows carrying the four messages per frame.  
The messages are inserted on an availability basis into the four message rows shown in Figure 27,  
rows 3,6,7 and 8. The header is always placed into columns 1 and 2. The Message itself is always  
placed MSByte first into columns 3 – 34, in FIFO order. The CRC-16, calculated over the header  
and message, is placed into columns 35 and 36.  
If no message is available, internal hardware will automatically insert zeros into the message  
bytes. Even if no message is available (32 of 36 bytes), the header(2 of 36 bytes) can still be  
carrying valid bits for the far end, as such even if the message is invalid, the Header and CRC are  
still generated and inserted. The header’s Valid bit is not set as an indication to the far end to  
discard the message (not insert the null message into its RxFIFO).  
12.12 ILC CPU Operations  
12.12.1 Accessing the Transmit Message FIFO  
Access registers in the following order:  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-2010850, Issue 1  
149