NSE-8G™ Standard Product Data Sheet
Preliminary
Register 117h + N*20H: ILC Interrupt Reason Register
Bit
Type
Function
Unused
Reserved
RX_TIMEOUTI
RX_THRSHLDI
RX_OVFLWI
RX_LINK_CHGI
RX_PAGE_CHGI[1:0]
RX_OUSER0_CHGI
Default
X
000000000
0
0
0
0
0
0
Bit 31:0
Bit 15:7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2:1
Bit 0
R
R
R
R
R
R
R
This register contains the status of events that may be enabled to generate interrupts.
All bits in this register are cleared on read
RX_OUSER0_CHGI
A ‘1’ in this bit indicates that the last received value of the RX_USER[0] header bit has
changed from a ‘0’ to a ‘1’ from the previously received values. This bit is cleared on a read.
RX_PAGE_CHGI [1:0]
A ‘1’ in these bits indicates that the last received value of the corresponding RX_PAGE[1:0]
header bits has changed from the previously received values. These bits are cleared on read.
RX_LINK_CHGI
A ‘1’ in this bit indicates that the last received value of the LINK[1:0] header bits has
changed from the previously received values. This bit is cleared on a read.
RX_OVFLWI
This bit, when ‘1’, indicates a Receive FIFO Overflow. This bit is cleared on a read.
RX_THRSHLDI
This bit, when ‘1’, indicates a Receive FIFO Threshold reached. This bit is cleared on a read.
RX_TIMEOUTI
This bit, when ‘1’, indicates a Receive FIFO Timeout. This bit is cleared on read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
124
PMC [ PMC-SIERRA, INC ]
