NSE-8G™ Standard Product Data Sheet
Preliminary
PMCTST
The PMCTST bit is used to configure the NSE-8G for PMC's manufacturing tests. When
PMCTST is set to logic one, the NSE-8G microprocessor port becomes the test access port
used to run the PMC "canned" manufacturing test vectors. As well, the analog blocks are
placed in IDDQ mode = the digital circuitry within the analog blocks is held static The
PMCTST can be cleared by setting CSB to logic one or by writing logic zero to the bit.
PMCATST
The PMCATST bit is used to configure the analog portion of the NSE-8G for PMC's
manufacturing tests. The PMCATST bit can be cleared by setting both CSB to logic one and
RSTB to logic zero. PMCATST can also be cleared by writing logic zero to the bit.
11.2 JTAG Test Port
The NSE JTAG Test Access Port (TAP) allows access to the TAP controller and the four TAP
registers: instruction, bypass, device identification and boundary scan. Using the TAP, device
input logic levels can be read, device outputs can be forced, the device can be identified and the
device scan path can be bypassed. For more details on the JTAG port, please refer to the
Operations section.
Table 12 Instruction Register (Length - 3 bits)
Instructions
EXTEST
IDCODE
SAMPLE
BYPASS
BYPASS
STCTEST
BYPASS
BYPASS
Selected Register
Boundary Scan
Identification
Boundary Scan
Bypass
Bypass
Boundary Scan
Bypass
Instruction Codes, IR[2:0]
000
001
010
011
100
101
110
111
Bypass
Table 13 Identification Register
32 bits
Length
0H
Version Number
8620H
Part Number – NSE-20G
Part Number – NSE–8G
Manufacturer's Identification Code
Device Identification – NSE-20G
Device Identification – NSE-8G
8621H
0CDH
086200CDH
086210CDH
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
127
PMC [ PMC-SIERRA, INC ]
