NSE-8G™ Standard Product Data Sheet
Preliminary
Register 10DH + N*20H, TXLV and PISO Control
Bit
Type
Function
Unused
Default
Bit 31:12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
0
0
0
0
0
0
0
0
1
1
1
Reserved[8]
Reserved[7]
Reserved[6]
TXLV_ENB
PISO_ENB
Reserved[5]
Reserved[4]
Reserved[3]
Reserved[2]
Reserved[1]
Reserved[0]
ARSTB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ARSTB
The analog reset bit (ARSTB) resets the associated TXLV and PISO blocks. When ARSTB is
set to logic 0, the TXLV and PISO are reset.
Reserved[5:0]
The Reserved[3:0] bits must be set to the indicated default value for correct operation of the
NSE.
PISO_ENB
The PISO enable bit (PISO_ENB) controls the operation of the PISO block. PISO_ENB is set
to logic one to disable the PISO block. PISO_ENB is set to logic 0 to enable the PISO block.
TXLV_ENB
The TXLV enable bit (TXLV_ENB) controls the operation of TXLV block. TXLV_ENB is
set to logic one to disable the TXLV block. TXLV_ENB is set to logic 0 to enable the TXLV
block.
Reserved[8]
The Reserved[8] bit must be set to the indicated default value for correct operation of the
NSE.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
110
PMC [ PMC-SIERRA, INC ]
