NSE-8G™ Standard Product Data Sheet
Preliminary
Register 109H + N*20H, T8TE Interrupt Status
Bit
Bit 31:5
Type
Function
Unused
Default
X
Bit 4
Bit 3:0
R
FIFOERRI
Unused
0
X
These registers report the interrupt status for T8TE blocks #0 through #11.
FIFOERRI
The FIFO overrun/underrun error interrupt indication bit (FIFOERRI) reports a FIFO
overrun/underrun error event. FIFOERRI is set high when when FIFO logic detects FIFO
read and write pointers in close proximity to each other. FIFOERRI is cleared on a read to
this register when WCIMODE is logic 0. FIFOERRI is cleared on a write (of any value) to
this register when WCIMODE is logic one. INTB is asserted low when both FIFOERRE and
FIFOERRI are high. IF FIFOERRE is asserted, FIFOERRI must be cleared before INTB will
be reasserted.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
106
PMC [ PMC-SIERRA, INC ]
