NSE-8G™ Standard Product Data Sheet
Preliminary
TX_MSG_LVL[3:0]
This indicates the current number of messages in the TXFIFO.
Table 7 TX FIFO Message Level
TX_MSG_LVL[3:0]
Number of messages
0000
:
0
:
1000
8
Values greater than 1000 will not occur. The number of free messages available in the FIFO is
given by (8 – TX_MSG_LVL).
IUSER
This bits are a reflection of the IUSER[2:0]. These reflect the USER bits that will be
transmitted in subsequent message headers. There is no default value for these bits as they are
device dependant.
IPAGE
This bits are a reflection of the IPAGE[1:0. These reflect the PAGE bits that will be
transmitted in subsequent message headers. There is no default value for these bits as they are
device dependant.
TX_LINK[1:0]
These bits reflect the last written value of the TX_LINK field of the TX Control register. The
upper byte of this register therefore reflects all of the configurable bits of the message
Header1 byte.
TX_MSG_LVL_VALID
This bit indicates that the value of TX_MSG_LVL is valid. When read with a ‘0’ this register
should be re-read until TX_MSG_LVL_VALID is a ‘1’. This bit will be clear for only
approximately 0.3% of time.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
114
PMC [ PMC-SIERRA, INC ]
