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PM8621 参数 Datasheet PDF下载

PM8621图片预览
型号: PM8621
PDF下载: 下载PDF文件 查看货源
内容描述: NSE- 8G⑩标准产品数据表初步 [NSE-8G⑩ Standard Product Data Sheet Preliminary]
分类和应用:
文件页数/大小: 184 页 / 957 K
品牌: PMC [ PMC-SIERRA, INC ]
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NSE-8G™ Standard Product Data Sheet  
Preliminary  
Register 112h + N*20H, ILC Transmit Misc.Status and FIFO Synch Register  
Bit  
Bit 31:16  
Type  
Function  
Unused  
Default  
X
Bit 15  
R
R
R
R
R
R
R
W
TX_MSG_LVL_VALID  
TX_LINK[1:0]  
IPAGE[1:0]  
IUSER[2:0]  
Reserved  
TX_MSG_LVL[3:0]  
TX_FI_BUSY  
TX_XFER_SYNC  
N/A  
00  
N/A  
N/A  
00  
0000  
0
0
Bit 14:13  
Bit 12:11  
Bit 10:8  
Bit 7:6  
Bit 5:2  
Bit 1  
Bit 0  
This register serves a dual purpose dependant on whether it is being read or written.  
When it is read it returns the status for the Message Transmit Channel.  
When it is written (with 0001h) to it is used it synchronize the Transmit FIFO to the start of a  
message boundary.  
TX_XFER_SYNC  
Writing ‘1’ to this bit initializes the next write sequence to be to the beginning of the next  
message. After a ‘1’ had been written successive writes to the Transmit FIFO will be to  
location zero of the next available slot. If a partial message has been written,  
TX_XFER_SYNC indicates that the current message is complete and that subsequent writes  
will be to the next message. If more than 32 bytes are written, the 33rd byte will be the first  
byte of the next message. The purpose of this bit is to unambiguously align the message  
boundaries. Another use would be to abandon the current write and move the write pointer to  
the beginning of the next message. (Previous message data will remain in the unwritten  
portion of the message being abandoned, which will have to be ignored by the receiving  
software).  
If the message FIFO pointers are already at a message boundary then writing this bit to a ‘1’  
will have no affect.  
On reads this bit is always returned as a ‘0’.  
TX_FI_BUSY  
This bit indicates that the internal hardware is transferring the data from the Transmit FIFO  
registers (TDAT) into the internal RAM. This bit need not be read by software if the time  
interval between successive 32 bit transfers is greater than 3 SYSCLK cycles.  
User and Page bits are a copy of the User bits received, and being transmitted in 0Ch. These  
allow one read in the 32 bit device to gain a snapshot of the entire ILC.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-2010850, Issue 1  
113  
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