NSE-8G™ Standard Product Data Sheet
Preliminary
Register 108H + N*20H, T8TE Control and Status
Bit
Type
Function
Unused
Reserved[1]
FIFOERRE
TPINS
Reserved[0]
CENTER
DLCV
Default
Bit 31:6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
0
0
0
1
0
R/W
R/W
R/W
R/W
W
R/W
These registers provide, control and report the status of the T8TE blocks.
Reserved[1:0]
The Reserved bit must be set to the indicated default value for correct operation of the NSE.
DLCV
The diagnose line code violation bit (DLCV) controls the insertion of line code violation in
the outgoing data stream. While DLCV is logic one and TCBMODE is logic 0, the
transmitted 8B/10B codes are inverted. This will result in at least one disparity error at a
receive 8B/10B decoder. When the NSE-8G is configured with TCBMODE logic one, and
DLCV logic one, 8B/10B data characters are inverted while the TeleCombus control
characters are not inverted. When DLCV is logic 0, no code inversion is performed.
CENTER
The FIFO centering control bit (CENTER) controls the separation of the T8TE FIFO read
and write pointers. CENTER is a write only bit. When a logic high is written to CENTER,
and the current FIFO depth is not in the range of 3, 4 or 5 characters, the FIFO depth is forced
to be four 8B/10B characters deep, with a momentary data corruption. Writing to the
CENTER bit when the FIFO depth is in the 3, 4 or 5 character range produces no effect.
CENTER always returns a logic low when read.
This bit must be set after CSU lock has been achieved to properly center the FIFO.
TPINS
The Test Pattern Insertion (TPINS) controls the insertion of test pattern in the outgoing data
stream for jitter testing purpose. When this bit is set high, TP[9:0] in the T8TE Test Pattern
register is selected for output.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
104
PMC [ PMC-SIERRA, INC ]
